Modifying work function of a metal film with a plasma process

ABSTRACT

A sequential plasma process is employed to enable the modification of the work function of a p-type metal layer in a metal gate structure. The sequential plasma process includes a plasma hydrogenation and a plasma process that includes electronegative species. The sequential plasma process is performed on a p-type metal layer in a film stack, thereby replacing suboxides and/or other non-stoichiometrically combined electronegative atoms disposed on or within layers of the film stack with stoichiometrically combined electronegative atoms, such as O atoms. As a result, the work function of the p-type metal layer can be modified without changing a thickness of the p-type metal layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/874,132, filed Jan. 18, 2018, which claims benefit of U.S.Provisional Patent Application Ser. No. 62/451,457, filed Jan. 27, 2017,which is herein incorporated by reference in its entirety.

BACKGROUND Field

Embodiments described herein generally relate to a method and apparatusfor processing semiconductor substrates, and more particularly, tomodifying a work function of a metal film processing.

Description of the Related Art

In a field-effect transistor (FET), threshold voltage is the minimumgate-to-source voltage differential required to create a conducting pathbetween the source and drain terminals and thereby turn the FET on. Thatis, when the gate voltage, i.e., the voltage applied to the gate of theFET, is above the threshold voltage, there are sufficient electrons inthe channel of the FET at the oxide-silicon interface to create alow-resistance channel in which charge can flow between the source andthe drain. Conversely, when the gate voltage is below the thresholdvoltage, the transistor is off, in which case there is no currentbetween the source and the drain of the transistor, except for leakagecurrent.

Since the threshold voltage determines the requirements for turning atransistor on or off, precise control of the threshold voltage isimportant in designing a properly operating transistor. As iswell-known, threshold voltage of a transistor is a function of thethickness and dielectric constant of the transistor gate dielectric.Consequently, one technique for designing a transistor to operate with aparticular threshold voltage involves scaling the gate dielectricthickness downward, i.e. reducing the dielectric thickness proportionalto reductions in other important transistor dimensions, such astransistor length and width.

However, as transistors are reduced in size with each technology node,precise control of threshold voltage by scaling gate dielectricthickness can be impracticable. Specifically, with a linear reduction ofthe thickness of the conventional oxide/oxynitride dielectric layer insome FETs, there is an exponential increase in gate leakage, resultingin increased power consumption. Furthermore, the thickness of thedielectric layer is now close to a few atomic layers, raisingreliability concerns. Thus, adjusting threshold voltage in a transistorby continued downward scaling of gate dielectric thickness isproblematic.

Threshold voltage is also a function of the thickness and work functionof the gate conductor material. Thus, another technique for controllingthe threshold voltage of a particular transistor involves using a gateconductor material that has a work function close to a target value,and, in some cases, selecting the deposited thickness of the gateconductor material to fine-tune the effective work function of the gateconductor material to the target value. For example, titanium nitride(TiN), having a work function value of about 4.6 eV, is commonlyemployed as a gate conductor material in some metal gate structures.Since the work function of a deposited TiN layer varies with thethickness of the deposited layer, the work function of TiN can be tunedfrom about 4.5 eV to about 4.7 eV.

However, as transistors are reduced in size with each technology node,reducing the thickness of such a TiN layer to decrease the effectivework function of the TiN layer is not be a viable option. For instance,with TiN layers in metal gate structures currently in the 10-20 Å range,a further decrease in thickness may result in a TiN layer of only a fewatomic layers. Thus, adjusting threshold voltage in a transistor byreducing metal gate material thickness is also problematic.

Accordingly, there is a need in the art for improved techniques tomodify threshold voltage of a transistor.

SUMMARY

Embodiments described herein generally relate to plasma processing of ametal layer to modify a work function value of the metal layer. In oneembodiment, a method of forming a transistor includes depositing ahigh-k dielectric layer over a surface of a semiconductor material,wherein the surface of the semiconductor material has a first workfunction value, after depositing the high-k dielectric layer, depositinga p-type metal layer over the semiconductor material and the high-kdielectric layer, wherein the p-type metal layer has an exposed surfaceand a second work function value, exposing the exposed surface of thep-type metal layer to plasma-excited electronegative species to changethe first work function value to a third work function value, whereinthe third work function value is between the first work function valueand the second work.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 sets forth an energy diagram depicting various allowed energylevels of electrons in a metal and in a semiconductor.

FIG. 2 illustrates a cross-sectional view of a metal gate structureformed according to an embodiment of the disclosure.

FIGS. 3A-3E are schematic views of a p-type metal layer within a metalgate structure at various stages of the fabrication of metal gatestructure, according to an embodiment of the disclosure.

FIG. 4 is a graph of an X-ray Photoelectron Spectroscopy (XPS) spectrumfor a deposited TiN film that is not treated with a plasma oxidationprocess and an XPS spectrum for a similar deposited TiN film aftertreatment with a plasma oxidation process, according to an embodiment ofthe disclosure.

FIG. 5 is a schematic cross sectional view of a plasma processingchamber configured to implement one or more aspects of the presentdisclosure.

FIG. 6 is a top plan view of a multi-chamber processing systemconfigured to implement one or more aspects of the present disclosure.

FIG. 7 sets forth a flow chart of process steps for modifying the workfunction of a metal layer in a metal gate structure, according tovarious embodiments of the disclosure.

FIGS. 8A-8E are schematic cross-sectional views of a semiconductordevice corresponding to different stages of the process of FIG. 7,according to various embodiments of the disclosure.

FIG. 9 sets forth a bar graph that compares measured flatband voltage(W) shift for a p-type metal layer after various treatments.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

DETAILED DESCRIPTION

Embodiments described herein generally relate to a method and apparatusfor modifying the work function of a metal layer in a conductivestructure, such as a metal gate structure. In the embodiments, a metallayer that is included in the conductive structure is exposed to plasmathat includes one or more plasma-excited, electronegative species. Theone or more electronegative species are incorporated into the metallayer, and thereby modify the work function of the metal layer. As aresult, the threshold voltage of a transistor that includes such a metalgate structure can be adjusted without changing the thickness of themetal layer.

In various embodiments, the electronegative species incorporated intothe metal layer are combined stoichiometrically with the metal atoms inthe lattice of the metal layer, so that molecules formed by theelectronegative species and metal atoms in the metal layer areelectroneutral. For example, in a titanium (Ti) metal layer exposed tooxygen—(O) containing plasma-excited species, O atoms combine with Tiatoms to form titanium dioxide (TiO₂), which is an electroneutralmolecule. By contrast, O atoms that combine with Ti in the metal layervia exposure to air and/or via atmospheric anneal processes aretypically suboxides (i.e., metal-rich), and are thereforeelectropositive. The incorporation and/or formation of electronegativespecies in a metal layer of a metal gate structure has been shown toalter the work function of the metal layer. The work function of a metallayer is described in greater detail below in conjunction with FIG. 1.

Work Function and Threshold Voltage

FIG. 1 sets forth an energy diagram 100 depicting various allowed energylevels of electrons in a metal 101 and electrons in a semiconductor 102.For example, metal 101 may be a TiN layer in a p-metal gate structure ofa transistor, and semiconductor 102 may be a channel of the transistorthat is formed from silicon (Si) and is disposed proximate the p-metalgate structure.

As shown, energy diagram 100 includes a free-electron energy E₀, whichis a reference level for energy representing energy that an electron hasif it is free of the influence of metal 101 or semiconductor 102. Inaddition, energy diagram 100 shows a Fermi energy E_(f,metal) for metal101 and a Fermi energy E_(f,semicon) for semiconductor 102, where theFermi energy refers to the energy of the highest occupied electron whenthe system (i.e., a bulk portion of metal 101 or a bulk portion ofsemiconductor 102) is in the ground state. Also shown are a metal workfunction φ_(m) for metal 101 and a semiconductor work function φ_(s) forsemiconductor 102, where the work function of a particular material isthe difference between the free-electron energy E₀ and the Fermi energyof that particular material. For semiconductor 102, energy diagram 100also shows the conductance band edge E₀ and the valence band edge E_(v).

As noted above, the threshold voltage of a transistor is a function ofthe work function of the gate conductor material. Thus, when metal 101is the gate conductor metal of a transistor, by modifying metal workfunction φ_(m) of material 101, the threshold voltage of the transistorcan be adjusted. More specifically, for a transistor with a metal gateformed by metal 101 and a channel formed by semiconductor 102, thethreshold voltage of the transistor can be adjusted by moving the workfunction φ_(m) value closer to the conductance band edge E_(c) or tovalence band edge E_(v).

As is known in the art, changing the thickness of some metal layers canalter the work function of the metal. However, given the physicalconstraints for fabricating transistors at smaller technology nodes,such as the 22 nm technology node and beyond (e.g., smaller devicesizes), changing the thickness of a constituent metal layer of atransistor to modify the work function of the metal layer is generallyno longer feasible. Furthermore, for very thin layers of a metal, suchas a few 10 s of nanometers, the work function of the metal may varysignificantly from that of a conventional sized thicker layer of thesame metal. This is likely due to the fact that such thin layers consistof such a small number of metal atoms that cannot donate sufficientelectrons to behave in the same way as a bulk region of a thicker metallayer. Thus, in many cases, at smaller technology nodes, the workfunction of certain metal layers may actually vary away from a desiredvalue previously achieved for the same metal material in largertransistors. According to embodiments of the disclosure, the workfunction of a metal layer in a metal gate structure is modified by beingexposed to plasma that includes one or more plasma-excited,electronegative species. Thus, both of the above issues associated withthe work function of very thin metal layers in a metal gate structure ofa transistor can be addressed. One such metal gate structure isillustrated in FIG. 2.

Metal Gate Structure with Modified Work Function

FIG. 2 illustrates a cross-sectional view of a metal gate structure 200formed according to an embodiment of the disclosure. Metal gatestructure 200 may be any portion of a semiconductor device that isconfigured to conduct electrical current and benefits from having aspecific work function. In the embodiment illustrated in FIG. 2, metalgate structure 200 is depicted as a conductive structure for providingelectrical current or voltage to a gate region of the semiconductordevice. As such, metal gate structure 200 is formed on a semiconductorsubstrate 201 as part of an FET, such as a metal-oxide-semiconductorfield-effect transistor (MOSFET). More specifically, metal gatestructure 200 is configured as a metal gate electrode of a pMOSFET, andconsequently includes one or more p-type metal layers, as opposed ton-type metal layers.

Metal gate structure 200 is a stack of multiple material layers formedon a semiconductor substrate 201 and includes, for example, aninterfacial layer 202 disposed on semiconductor substrate 201, a high-kdielectric layer 203 disposed on the interfacial layer 202, a p-typemetal capping layer 204 disposed on the high-k dielectric layer 203, anda p-type metal gate electrode layer 205 disposed on the p-type metalcapping layer 204. In the embodiment illustrated in FIG. 2, the variouslayers of the metal gate structure 200 are depicted as a simple filmstack formed on the semiconductor substrate 201. In practice, metal gatestructure 200 may be formed in a contact well or other cavity formed inan insulating or dielectric material, such as silicon dioxide (SiO₂),silicon nitride (Si₃N₄), or multiple layers thereof. Thus, one or moreof interfacial layer 202, high-k dielectric layer 203, p-type metalcapping layer 204, and p-type metal gate electrode layer 205 may bematerial layers that are conformally deposited within such a cavity.

Semiconductor substrate 201 may be any suitable semiconductor substrateon which metal gate structure 200 can be formed. As such, semiconductorsubstrate 201 may be formed from any suitable semiconductor materialincluding, but not limited to Si (Si), Ge (germanium), silicon-germanium(Si—Ge), silicon-germanium-carbon (SiGeC), gallium (Ga), galliumarsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and allother III/V or II/VI compound semiconductors. Alternatively oradditionally, semiconductor substrate 201 may be a layered semiconductorsuch as, for example, Si/Si—Ge, a semiconductor-on-insulator (SOI) or aSi—Ge-on-insulator (SiGOI).

In some embodiments, metal gate structure 200 is configured as a metalgate electrode of a pMOSFET. In such embodiments, the portion ofsemiconductor substrate 201 proximate to the interfacial layer 202 isconfigured as a channel region of an FET, and therefore includes ann-type semiconductor material.

The interfacial layer 202 is disposed on semiconductor substrate 201between semiconductor substrate 201 and high-k dielectric layer 203, andis configured as an interfacial oxide layer suitable for application inmetal gate structure 200. In embodiments in which semiconductorsubstrate 201 includes a Si-containing material, the interfacial layer202 may include silicon oxide (SiO_(x)), silicon oxynitride (SiNO,Si₂NO, Si₂N₂O), and/or a nitrided silicon oxide. In embodiments in whichsemiconductor substrate 201 is other than a Si-containing semiconductormaterial, the interfacial layer 202 may comprise a semiconductor oxide,a semiconducting oxynitride and/or a nitrided semiconducting oxide.

The interfacial layer 202 may be formed via any suitable thermal or wetgrowing technique, for example, oxidation or oxynitridation. Forexample, and without limitation, the interfacial layer 202 may be formedby a wet chemical oxidation process that includes treating a cleanedsurface of semiconductor substrate 201, such as an HF-last treatedsemiconductor surface, with a mixture of ammonium hydroxide, hydrogenperoxide and water. Alternatively, the interfacial layer 202 may beformed by treating an HF-last treated semiconductor surface in ozonatedaqueous solutions. Alternatively, the interfacial layer 202 may beformed by any suitable thermal oxidation technique.

High-k dielectric layer 203 may be a gate dielectric layer or otherdielectric layer in metal gate structure 200, and includes a so-called“high-k dielectric” material. More specifically, high-k dielectric layer203 includes one or more materials that have a dielectric constantgreater than that of SiO₂, such as a material having a dielectricconstant of at least about 4.0, or ideally at least about 10.0. Inaddition, the high-k dielectric material included in high-k dielectriclayer 203 is suitable for use in an integrated circuit. Thus, inaddition to a high dielectric constant, the one or more high-kdielectric materials included in high-k dielectric layer 203 alsoideally have the ability to prevent diffusion of dopants, few electricaldefects that can compromise breakdown performance, good thermalstability, and high recrystallization temperature. Examples of suchhigh-k dielectric materials suitable for use in high-k dielectric layer203 include, without limitation, silicon nitride, silicon oxynitride,metal oxides, metal nitrides, metal oxynitrides and/or metal silicates.In some embodiments, high-k dielectric layer 203 includes one or more ofhafnium oxide (Hf_(x)O_(y)), zirconium oxide (ZrO₂), hafnium silicateoxides (Hf_(x)Si_(1-x)O_(y)) or other hafnium-based dielectrics,lanthanum oxides (La₂O₃), aluminum oxide (Al₂O₃), titanium oxide (TiO₂),strontium titanate (SrTiO₃), lanthanum aluminate (LaAlO₃), yttrium oxide(Y₂O₃), hafnium silicate oxides (Hf_(x)Si_(1-x)O_(y)), lanthanum oxides(La₂O₃), and/or multilayered stacks thereof.

High-k dielectric layer 203 may be formed via any suitable depositionmethod, including a thermal growth process such as, for example, anoxidation, nitridization or oxynitridization process. Alternatively,high-k dielectric layer 203 may be formed by one or more depositionprocess including, but not limited to chemical vapor deposition (CVD),plasma enhanced chemical vapor deposition (PECVD), metalorgano chemicalvapor deposition (MOCVD), atomic layer deposition (ALD), evaporation,reactive sputtering, chemical solution deposition and/or any combinationof thereof.

P-type metal capping layer 204 is a p-type metal layer disposed onhigh-k dielectric layer 203 that is typically configured as anelectrically conductive protective layer on high-k dielectric layer 203.In some embodiments, p-type metal capping layer 204 is configured toprevent unwanted oxidation of semiconductor substrate 201 and/or high-kdielectric layer 203. In some embodiments, p-type metal capping layer204 includes a metal nitride, such as TiN, tantalum nitride (TaN), andthe like.

P-type metal capping layer 204 may be formed via any suitable depositionmethod, including but not limited to physical vapor deposition (PVD),chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), metalorgano chemical vapor deposition (MOCVD),atomic layer deposition (ALD), evaporation, reactive sputtering,chemical solution deposition and/or any combination of thereof.

P-type metal gate electrode layer 205 is a metal layer formed on p-typemetal capping layer 204, and includes one or more deposited metallayers. P-type metal gate electrode layer 205 may be formed via anysuitable deposition method, including, but not limited to, CVD, PECVD,MOCVD, ALD, evaporation, reactive sputtering, chemical solutiondeposition and/or any combination of thereof. In some embodiments,p-type metal gate electrode layer 205 is a p-type metal gate material,such as TiN. Other suitable p-type metals may also be used in p-typemetal gate electrode layer 205.

In some embodiments, p-type metal gate electrode layer 205 is configuredas a gate electrode and/or work function metal of metal gate structure200. In such embodiments, the one or more metal layers included inp-type metal gate electrode layer 205 are selected to have a gateelectrode work function value that facilitates operation of metal gatestructure 200 and of a semiconductor device in which metal gatestructure 200 is included.

In some embodiments, p-type metal capping layer 204 and p-type metalgate electrode layer 205 are very thin films. For example, in oneembodiment of metal gate structure 200, p-type metal capping layer 204is a TiN layer having a thickness 204A of about 5 nm to about 15 nm,while p-type metal gate electrode layer 205 is a TiN layer having athickness 205A of about 20 nm to about 40 nm. Consequently, changes tothickness 204A or 205A sufficient to modify the work function of p-typemetal capping layer 204 or p-type metal gate electrode layer 205 cannegatively impact the operation of a transistor that includes metal gatestructure 200. In addition, conventional metal layers having a thickness204A or 205A may have a different work function than a conventionalsized thicker layer of the same metal, and as a result can significantlydegrade performance or operation of the transistor. According to variousembodiments, the work function of p-type metal capping layer 204 orp-type metal gate electrode layer 205 is modified by exposure toelectronegative, plasma-excited species, and not by varying thethickness 204A or 205A.

Physical Model of Modifying Work Function with a Plasma Process

FIGS. 3A-3E are schematic views of a p-type metal layer 350 within metalgate structure 200 at various stages of the fabrication of metal gatestructure 200, according to an embodiment of the disclosure. P-typemetal layer 350 may represent p-type metal capping layer 204, p-typemetal gate electrode layer 205, or any other p-type metal layer includedin metal gate structure 200. It is noted that each different p-typemetal element suitable for use in metal layer 350 generally has adifferent three-dimensional crystalline structure or structures.Consequently, one of ordinary skill in the art will readily understandthat FIGS. 3A-3E are schematic representations of the crystallinestructure of metal layer 350, and are not intended to depict anyparticular crystalline structure of metal layer 350, such as abody-centered cubic (bcc) structure, a face-centered cubic (fcc)structure, or the like. Thus, the crystalline structure of metal layer350 is not limited to that illustrated in FIGS. 3A-3E, and may have anyother possible crystalline structure or surface termination.

In FIG. 3A, a portion 300 of p-type metal layer 350 is schematicallyillustrated immediately after p-type metal layer 350 has been depositedand prior to portion 300 being exposed to air. For example, FIG. 3A maydepict p-type metal capping layer 204 after being deposited on high-kdielectric layer 203 or p-type metal gate electrode layer 205 afterbeing deposited on metal capping layer 204. Portion 300 includes asurface 301 of portion 300 that will undergo a plasma treatment asdescribed herein. In the embodiment illustrated in FIG. 3A, p-type metallayer 350 is a TiN layer, and is primarily made up of Ti and N atoms. Inother embodiments, p-type metal layer 350 may be any other p-type metalsuitable for use in metal gate structure 200.

In addition, portion 300 includes a low concentration of bulk O atoms311 (cross-hatched), typically disposed in a bulk region of portion 300below surface 301. The bulk O atoms 311 may be incorporated bycontamination found in the processing environment during the depositionprocess used to form portion 300. Further, portion 300 generallyincludes vacancies 313, which are sites within the crystal lattice ofportion 300 where an atom is missing. Vacancies 313 are locations atwhich additional oxidation within portion 300 may take place when p-typemetal layer 350 is exposed to air. It is noted that when p-type metallayer 350 is formed by an atomic layer deposition (ALD) process,vacancies 313 are relatively common due to the film nucleation andgrowth mechanisms found in an ALD process versus a traditional chemicalvapor deposition (CVD) or physical vapor deposition (PVD) process. Thusone or more of the embodiments of the disclosure provide herein mayprovide significant benefits when used on films formed by an ALD processversus conventional PVD or CVD type processes.

In FIG. 3B, portion 300 is illustrated after being removed from theprocessing system that deposited p-type metal layer 350. For example,semiconductor substrate 201 on which portion 300 is formed may beexposed to air in preparation for a thermal anneal process. Typically,conventional thermal processing chambers, such as anneal processchambers, are performed in different processing systems from theprocessing systems that are used to form p-type metal layer 350, due toa difference in the required cleanliness, thermal management control andvacuum level requirements needed to form most advanced device nodesapplications today. Thus, in FIG. 3B, portion 300 is illustrated afterbeing exposed to air. As shown, surface 301 has been partially oxidized,with surface O atoms 312 occupying most or all of the vacancies 313disposed on surface 301. In some cases, some of the vacancies 313disposed within portion 300 are occupied with bulk O atoms 311 as aresult of exposure of portion 300 to air.

In FIG. 3C, portion 300 is illustrated after undergoing a thermal annealprocess, for example to densify p-type metal layer 350 after beingdeposited. Some or all of the remaining vacancies 313 are filled withbulk O atoms 311 or surface O atoms 312. In some embodiments, bulk Oatoms 311 may also displace a portion of the N atoms disposed withinportion 300. Thus, the anneal process generally increases the number ofboth bulk O atoms 311 and surface O atoms 312 in portion 300.

It is noted that, in general, bulk O atoms 311 and surface O atoms 312that have combined with Ti atoms in p-type metal layer 350 via exposureto air and/or via atmospheric anneal processes typically form suboxides,i.e., metal-rich compounds. Bulk O atoms 311 and surface O atoms 312 insuch suboxides are not stoichiometrically combined with the metal atomsin p-type metal layer 350. As a result, the binding energies of atomsassociated with the suboxide bonds between bulk O atoms 311/surface Oatoms 312 and the Ti atoms in p-type metal layer 350 are quantitativelydifferent than the binding energies of stoichiometrically combined Oatoms and the metal atoms in p-type metal layer 350, and typically havedifferent bond orientation and arrangement between the O atoms and themetal atoms in p-type metal layer 350. In addition, the binding energiesassociated with the above-described suboxide bonds are generally lowerthan the binding energies associated with stoichiometrically combined Oatoms and the metal atoms in p-type metal layer 350.

In FIG. 3D, portion 300 is illustrated after being exposed to hydrogenatoms that react with bulk O atoms 311 and/or surface O atoms 312included in portion 300, according to various embodiments of thedisclosure. In some embodiments, bulk O atoms 311 and/or surface O atoms312 react with hydrogen atoms from a hydrogen-containing plasma as partof a plasma hydrogenation process. The plasma hydrogenation process maybe performed in a suitable plasma processing chamber under certainprocessing conditions. An exemplary plasma processing chamber and plasmaprocessing conditions are each described below for the plasmahydrogenation process. As shown, the hydrogenation process reduces orotherwise removes all or substantially all of the surface O atoms 312from surface 301, leaving vacancies 313 behind. Moreover, the plasmahydrogenation process may also remove some or all bulk O atoms 311disposed below surface 301.

In FIG. 3E, portion 300 is illustrated after undergoing a plasmaoxidation process, according to various embodiments of the disclosure.The plasma oxidation process may be performed in a suitable plasmaprocessing chamber under certain processing conditions, and an exemplaryplasma processing chamber and plasma processing conditions are eachdescribed below for the plasma oxidation process. In some embodiments,the plasma oxidation process may be performed in the same plasmaprocessing chamber that performs the plasma hydrogenation process. Inaddition, no air break occurs between the plasma or thermalhydrogenation process and the plasma oxidation process. That is, portion300 is not exposed to air after the plasma hydrogenation process andbefore the plasma oxidation process.

As shown, the plasma oxidation process causes vacancies 313 to be filledwith plasma-deposited O atoms 314. Unlike bulk O atoms 311 or surface Oatoms 312, most or all of plasma-deposited O atoms 314 arestoichiometrically combined with atoms in p-type metal layer 350, forexample with Ti atoms as TO₂. It is noted that the binding energies ofstoichiometrically combined plasma-deposited O atoms 314 to the metalatoms in p-type metal layer 350 are quantitatively different than thebinding energies of atoms associated with the suboxide bonds betweenbulk O atoms 311/surface O atoms 312 and the Ti atoms in p-type metallayer 350. This difference in binding energies is illustrated in FIG. 4.

FIG. 4 is a graph of an X-ray Photoelectron Spectroscopy (XPS) spectrum410 for a deposited TiN film that is not treated with a plasma oxidationprocess and an XPS spectrum 420 for a similar deposited TiN film aftertreatment with a plasma oxidation process and then exposure to air,according to an embodiment of the disclosure. In some embodiments, theplasma oxidation process includes a sequential plasma hydrogenationprocess followed by a plasma oxidation process, each of which isdescribed below in conjunction with FIG. 5.

As is well-known in the art, an XPS spectrum of a TiN film may includemultiple peaks, each indicating a different relative concentration ofdifferent titanium-containing materials. For example, a sharp Ti—O peakat a binding energy of approximately 458.5 eV, indicates the presence ofTi—O bonds and, therefore, the presence of O atoms stoichiometricallycombined with Ti atoms, whereas a sharp Ti—N peak at a binding energy ofapproximately 454.9 eV generally indicates the presence of Ti—N bondsand, therefore, the presence of nitrogen (N) atoms stoichiometricallycombined with Ti atoms. Furthermore, the presence of a broader peak thatis somewhat lower than the binding energy Ti—O bonds, such as peak 430,can indicate the presence of various suboxides of titanium.

XPS spectrum 410 is associated with a deposited TiN film after beingdeposited and exposed to air, and XPS spectrum 420 is associated with asimilar TiN film after being deposited and exposed to air, and thenundergoing a plasma hydrogenation process followed by a plasma oxidationprocess, as described herein. Thus, XPS spectrum 410 is associated witha surface of a TiN film similar to surface 301 illustrated in FIG. 3B,whereas XPS spectrum 420 is associated with a surface of a TiN filmsimilar to surface 301 illustrated in FIG. 3E.

As shown in FIG. 4, the peak associated with Ti—O bonds is significantlyhigher in XPS spectrum 420 than in XPS spectrum 410. The higher Ti—Opeak in XPS spectrum 420 indicates that treating a TiN film with theplasma hydrogenation process followed by the plasma oxidation processresults in an increase in the presence of O atoms in the treated TiNfilm that are stoichiometrically combined with Ti atoms. Conversely,peak 430, which is associated with various titanium suboxides, ispresent in XPS spectrum 410 and largely absent in XPS spectrum 420.Thus, peak 430 indicates the presence of significantly more suboxides inthe TiN film that has not undergone the plasma hydrogentation and plasmaoxidation processes.

System Overview for Modifying Work Function of a Metal Layer

FIG. 5 is a schematic cross sectional view of a plasma processingchamber 500 configured to implement one or more aspects of the presentdisclosure. Plasma processing chamber 500 may be any suitable plasmaprocessing chamber, such as an inductively coupled plasma (ICP)processing chamber. As shown in FIG. 5, processing chamber 500 mayinclude a chamber wall 506, a chamber lid 508 and a substrate supportpedestal 504 disposed within the chamber wall 506. Typically, chamberwall 506 is coupled to an electrical ground 516. Chamber lid 508 may becomposed of any suitable dielectric, such as quartz. For someembodiments, dielectric lid 508 may assume a different shape (e.g.,dome-shaped). In some embodiments, chamber lid 508 may be coated with aceramic coating, such as an yttrium containing oxide, for protectionfrom plasma species. In one embodiment, the ceramic coating is a highperformance material (HPM) that is composed of a compound Y₄Al₂O₉ and asolid solution Y_(2-x)Zr_(x)O₃ (Y₂O₃—ZrO₂ solid solution). The ceramiccoating may have a thickness ranging from about 100 microns to about 300microns, such as about 200 microns.

Above chamber lid 508, a radio frequency (RF) antenna including at leastone inductive coil element 510 may be disposed (two coaxial coilelements are shown). In some embodiments, inductive coil elements 510may be disposed around at least a portion of chamber wall 506. One endof inductive coil element 510 may be coupled, through a first impedancematching network 512, to an RF power source 514, and the other end mayend may be connected to an electrical ground 517 as shown. Power source514 is typically capable of producing up to 10 kilowatts (kW) at atunable frequency in a range from 2 to 160 MHz, with 13.56 MHz being atypical operating frequency. The RF power supplied to inductive coilelements 510 may be pulsed (i.e., switched between an on and an offstate) or power cycled (i.e., varying a power input from a high level toa low level) at a frequency ranging from 1 to 100 kHz.

A shielding electrode 518 may be interposed between inductive coilelements 510 of the RF antenna and chamber lid 508. Shielding electrode518 may be alternately electrically floating or coupled to an electricalground 519 via any suitable means for making and breaking an electricalconnection, such as a switch 520 as illustrated in FIG. 5.

For some embodiments, a detector 522 may be attached to chamber wall 506to facilitate determining when a gas mixture within chamber 500 has beenenergized into plasma. Detector 522 may, for example, detect theradiation emitted by the excited gases or use optical emissionspectroscopy (OES) to measure the intensity of one or more wavelengthsof light associated with the generated plasma.

Pedestal 504 may be coupled, through a second impedance matching network524, to a biasing power source 526. Biasing power source 526 isgenerally capable of producing an RF signal having a tunable frequencyranging from 2 to 160 MHz and power between 0 and 10 kW, similar to RFpower source 514. Optionally, biasing power source 526 may be a directcurrent (DC) or pulsed DC source.

In operation, a substrate 528, such as a semiconductor substrate, isplaced on pedestal 504, and process gases are supplied from a gas panel530 through entry ports 532 to form a gaseous mixture 534. Typicalprocess gases that are used in one or more of the processes describedherein are described below. Entry ports 532 may be coated with theceramic coating, such as HPM. Gaseous mixture 534 is energized into aplasma 536 in processing chamber 500 by applying power from RF powersource 514. The pressure within the interior of processing chamber 500is controlled using a throttle valve 538 and a vacuum pump 540. In someembodiments, the temperature of chamber wall 506 may be controlled usingliquid-containing conduits (not shown) that run through chamber wall 506or heating elements embedded in chamber wall 506 (e.g., heatingcartridges or coils) or wrapped around processing chamber 500 (e.g.,heater wrap or tape).

The temperature of substrate 528 is controlled by stabilizing thetemperature of pedestal 504. In some embodiments, helium (He) gas from agas source 542 may be provided via a gas conduit 544 to channels (notshown) formed in the pedestal surface under substrate 528. The heliumgas facilitates heat transfer between pedestal 504 and substrate 528.During processing, pedestal 504 can be heated to a steady statetemperature, and then the helium gas facilitates uniform heating of thesubstrate 528. Pedestal 504 can be heated by a heating element (notshown), such as a resistive heater embedded within pedestal 504, or alamp generally aimed at pedestal 504 or substrate 528 when thereon.Using such thermal control, substrate 528 may be maintained at atemperature between about 20 to 350 degrees Celsius (° C.).

In order to allow for control of the components of processing chamber500 as described herein, a controller 546 may be provided. Controller546 may comprise a central processing unit (CPU) 548, a memory 550, andsupport circuits 552 for CPU 548. Controller 546 may interface with RFpower source 514, switch 520, detector 522, and biasing power source526.

Controller 546 may be any suitable type of general-purpose computerprocessor that can be used in an industrial setting for controllingvarious chambers and sub-processors. Memory 550, or othercomputer-readable medium, for CPU 548 may be one or more of any readilyavailable memory forms, such as random access memory (RAM), read onlymemory (ROM), a floppy disk, a hard disk, or any other form of digitalstorage, local or remote. Support circuits 552 may be coupled to CPU 548in an effort to support the processor in a conventional manner. Thesecircuits may include cache, power supplies, clock circuits, input/output(I/O) circuitry and subsystems, and the like. For some embodiments,control instructions for operating the processing chamber 500 toenergize and maintain a plasma may be stored in memory 550 as a softwareroutine. The software routine may also be stored and/or executed by asecond CPU (not shown) that is remotely located from the hardware beingcontrolled by CPU 548.

According to some embodiments of the disclosure, a plasma hydrogenationprocess, followed by a plasma oxidation process, hereinafter referred toas a “sequential hydrogenation/oxidation process,” is performed on ametal layer on the substrate to modify the work function of the metallayer. The sequential hydrogenation/oxidation process may include acapacitively coupled plasma process or an inductively coupled plasmaprocess. In some embodiments, plasma for the hydrogenation/oxidationprocess may be formed in a remote plasma source outside of processingchamber 500, and in other embodiments, the plasma for the plasma processmay be formed in-situ, i.e., in processing chamber 500.

In the plasma hydrogenation process, plasma-excited H radicals and/orions react with bulk O atoms 211 and/or surface O atoms 212 to createvacancies 213, as illustrated in FIG. 3D. In the oxidation process, Oradicals and/or ions occupy vacancies 213, and generally producestoichiometric oxides rather than suboxides, as illustrated in FIG. 3E.

When a metal layer to be treated with the herein describedhydrogenation/oxidation process is a thin film with a thickness of about200 Å or less, an ICP process is generally less likely to damage themetal nitride layer, either during hydrogenation or nitridization.Specifically, in an ICP process the plasma sheath is typically smallerthan that in a CCP chamber, and therefore ions traveling therethoughtypically have proportionally less energy, for example on the order of10 s of eV, such as 10 to 20 eV. By contrast, ions in a CCP chambertypically have energies on the order of 100 s of eVs (e.g., >200-400eV), and consequently can create significant damage to the metal nitridelayer. Furthermore, an ICP process can provide more oxygen removal froma metal nitride layer than by use of a CCP or remote plasma process, dueto the higher density of ions, radicals, and other plasma-excitedspecies generally formed in the an ICP processing chamber and inproximity to the substrate versus CCP and remote plasma sources used inother types of processing chambers. In comparison, a concentration ofradicals from CCP and remote plasma sources is relatively low.

In embodiments in which the plasma for the plasma process is formedin-situ, the plasma may be formed via inductive coil elements 510, firstimpedance matching network 512, RF power source 514, and, in someembodiments, second impedance matching network 524 and biasing powersource 526. In such embodiments, the plasma process may include theintroduction of one or more process gases into processing chamber 500that are selected to generate certain plasma species (i.e., ions,neutral atoms, and/or radicals). More specifically, in the case of theplasma hydrogenation process, the one or more process gases are selectedto generate plasma-excited hydrogen species, while in the case of theplasma oxidation process, the one or more process gases are selected togenerate plasma-excited oxygen species. Thus, for the plasmahydrogenation process, the one or more process gases may includehydrogen (H₂), and/or other hydrogen-containing gases, and for theplasma oxidation process, the one or more process gases may includeoxygen (O₂), and/or other oxygen-containing gases. Alternatively oradditionally, the plasma process may include the introduction of one ormore carrier and/or inert gases into processing chamber 500, such asargon (Ar).

In some embodiments, the one or more process gases are energized by anRF power source, such as RF power source 514. The RF power may be pulsedat between 2% to 70% duty cycle and may range from about 100 W to about2500 W. The RF power may be a continuous wave ranging from about 100 Wto about 2500 W. The process chamber may have a chamber pressure rangingfrom about 10 mT to about 200 mT during the plasma process, while theprocess temperature, for example the temperature of pedestal 504, mayrange from 20° C. to about 500° C.

In an exemplary embodiment, a plasma hydrogenation process is performedat a process temperature that is between about 400° C. and about 500°C., a chamber pressure that is between about 5 mT and about 20 mT, an RFpower that is between about 1000 W and about 2000 W, and a biasingvoltage that is between about 175 V and about 250 V, with an H₂ flowthat is between about 20 sccm and about 40 sccm and an Ar flow that isbetween about 400 sccm and about 500 sccm for a period of time ofbetween about 50 seconds and about 300 seconds. Plasma-excited hydrogenspecies generated from the plasma inside process chamber 500 can reducesome or all oxides present on the exposed surface of a metal layer(e.g., p-type metal layer 350) of a partially formed conductivestructure (e.g., metal gate structure 200). In some embodiments, theplasma-excited hydrogen species can also reduce some or all O atomspresent in the bulk material of a metal nitride layer or other metallayers of the metal gate structure, such as p-type metal capping layer204. Such reduction of O atoms is described above in conjunction withFIG. 3D.

In another exemplary embodiment, a plasma oxidation process is performedat a process temperature that is between about 300° C. and about 500°C., a chamber pressure that is between about 5 mT and about 20 mT, an RFpower that is between about 100 W and about 2500 W, and a biasingvoltage that is between about 175 V and about 250 V, with an O₂ flowthat is between about 10 sccm and about 50 sccm, an N₂ flow that isbetween about 300 sccm and about 500 sccm, and an Ar flow that isbetween about 300 sccm and about 500 sccm for a period of time ofbetween about 50 seconds and about 300 seconds. Plasma-excited oxygenspecies generated from the plasma inside process chamber 500 can fillvacancies present on the exposed surface and in the bulk material of ametal layer or layers of the metal gate structure, such as p-type metallayer 350. Such oxidation is described above in conjunction with FIG.3E.

FIG. 6 is a top plan view of a multi-chamber processing system 600configured to implement one or more aspects of the present disclosure.Multi-chamber processing system 600 is configured to perform one or morefabrication processes on individual substrates, such as silicon wafers,for forming semiconductor devices. Multi-chamber processing system 600includes some or all of a transfer chamber 606, a buffer chamber 608,single wafer load locks 610 and 612, processing chambers 614, 616, 618,620, 622, and 624, preheating chambers 623 and 625, and robots 626 and628. Single wafer load locks 610 and 612 may include heating elements613 and are attached to buffer chamber 608. Processing chambers 614,616, 618, and 620 are attached to transfer chamber 606. Processingchambers 622 and 624 are attached to buffer chamber 608. The operationof multi-chamber processing system 600 is controlled by a computersystem 630. Computer system 630 may be any device or combination ofdevices configured to implement the inventive operations providedherein. As such, computer system 630 may be a controller or array ofcontrollers and/or a general purpose computer configured with softwarewhich, when executed, performs the inventive operations. One example ofa suitable multi-chamber processing system 600 is the Endura® CL Systemmanufactured by Applied Materials, Inc. of Santa Clara, Calif.

Each of processing chambers 614, 616, 618, 620, 622, and 624 may beconfigured to perform one or more process steps in the fabrication of aconductive structure in a semiconductor device, such as a contactstructure for a field-effect transistor (FET). More specifically,processing chambers 614, 616, 618, 620, 622, and 624 may include one ormore metal deposition chambers, surface cleaning and preparationchambers, thermal anneal and/or thermal hydrogenation chambers, andplasma hydrogenation/nitridization chambers.

In some embodiments multi-chamber processing system 600 may beconfigured to sequentially perform several process steps in thefabrication process of a metal gate structure. For example, a particularmetal gate structure may include a TiN capping layer that is formed on agate dielectric and is similar to p-type metal capping layer 204 in FIG.2, and a TiN work function layer, that is formed on the TiN cappinglayer and is similar to p-type metal electrode layer 205 in FIG. 2. Insuch embodiments, processing chamber 614 and/or 616 may be configured todeposit the TiN capping layer on the gate dielectric; processing chamber622 and/or 624 may be configured to densify the TiN capping layer byperforming a rapid thermal processing (RTP) or other thermal annealprocess on the TiN capping layer; processing chamber 618 may beconfigured to deposit the TiN work function layer; and processingchamber 620 may be configured to perform a hydrogenation processfollowed by an oxidation process. The sequential hydrogenation/oxidationprocess may be performed on an exposed surface of the TiN capping layeror on an exposed surface of the TiN work function layer. Thus, in suchembodiments, a metal gate structure that has a modified work functioncan be completed without an air break and the resulting unwantedformation of suboxides on one or more layers of the metal gatestructure.

In alternative embodiments, not all process steps for completing a metalgate structure are performed on a single multi-chamber processing system600. For example, in some embodiments, multi-chamber processing system600 may include metal deposition processing chambers for depositing oneor more p-type metal layers 350, while a thermal anneal process may beperformed on the p-type metal layer 350 via a different substrateprocessing system. In such embodiments, an air break occurs before thethermal anneal process, and it is known that such an air break canincrease the presence of O atoms, in the form of suboxides, on anexposed surface of the metal layer. However, prior to the air break, asequential plasma hydrogenation/plasma oxidation process can beperformed, since multi-chamber processing system 600 may be configuredwith both metal deposition chambers and one or more plasma processingchambers. Thus, multi-chamber processing system 600 can be configured toperform a sequential hydrogenation/oxidation process on a substrateafter deposition of p-type metal layer 350, but before the substrate isremoved from multi-chamber processing system 600 and exposed to air.Performing the sequential hydrogenation/oxidation process on an exposedsurface of p-type metal layer 350 prior to an air break can formstoichiometric oxides on and/or in p-type metal layer 350, and greatlyreduce formation of suboxides on the exposed surface during thesubsequent air break.

In some embodiments, multi-chamber processing system 600 may include oneor more thermal anneal and plasma processing chambers. In suchembodiments, a sequential hydrogenation/oxidation process can beperformed after the thermal anneal process, thereby removing O atomsintroduced by a pre-anneal air break and by the thermal anneal processitself. Typically, thermal annealing processes are not able to maintaindesirably low oxygen levels required for most advanced device nodes, dueto the high temperatures that the processing components (e.g., seals,process kit components, pumps, etc.) achieve during thermal processing.Thus, in such embodiments, p-type metal layer 350 is deposited in oneprocessing system, and the p-type metal layer 350 then undergoes thethermal anneal process and the sequential hydrogenation and oxidationprocess in a different processing system.

In some embodiments, multi-chamber processing system 600 may include oneor more metal deposition chambers configured to deposit p-type metal 350and one or more plasma processing chambers to perform a sequentialhydrogenation and oxidation process. In such embodiments, a sequentialhydrogenation and oxidation process can be performed after thedeposition of p-type metal layer 350 in a metal gate structure, therebyforming stoichiometric oxides on and in p-type metal layer 350.Consequently, the work function of p-type metal layer 350 is modified,and the formation of suboxides are on p-type metal layer 305 in asubsequent air break is greatly reduced. It is noted that in suchembodiments, no air break occurs between the deposition of p-type metallayer and the sequential hydrogenation and oxidation process.

In the embodiments set forth above, the work function of a metal layeris modified via a hydrogenation process followed by an oxidation processto stoichiometrically add O atoms to the metal layer. In the oxidationprocess, an exposed surface of the metal layer is exposed toplasma-excited oxygen species, such as O ions, O atoms, and/or Oradicals. In other embodiments, the work function of a metal layer ismodified via a hydrogenation process followed by a plasma process inwhich other electro-negative atoms are added to the metal layer insteadof O atoms. For example, such electro-negative atoms can includenitrogen, fluorine (F), and/or chlorine (CI). Furthermore, in someembodiments, such electro-negative atoms can include any atoms having aPaulding electronegativity of at least about 2.5, i.e., carbon (C)atoms, sulfur (S) atoms, selenium (Se) atoms, bromine (Br) atoms, iodine(I) atoms, and the like. In such embodiments, an exposed surface of themetal layer is exposed to plasma-excited, electronegative species, toadd atoms from the electronegative species to the metal layer andthereby modify the work function of the metal layer. As set forth abovewith respect to O atoms, addition of other electronegative species tothe metal layer via a plasma process generally results in thestoichiometric addition of the electronegative atoms to the metal layer.

In some embodiments, the plasma process in which electronegative atomsare added to the metal layer can be performed via plasma processingchamber 500. In such embodiments, the above-described plasma oxygenationprocess can be modified with one or more different process gases. Forexample, in embodiments in which F atoms are added to a metal layer viaexposure to plasma-excited, electronegative species, the process gasesmay include any fluorine-containing gas. In such embodiments, the plasmaprocess is performed at a process temperature that is between about 300°C. and about 500° C., a chamber pressure that is between about 5 mT andabout 20 mT, an RF power that is between about 1000 W and about 2500 W,and a biasing voltage that is between about 175 V and about 250 V, witha fluorine-containing process gas flow that is between about 10 sccm andabout 50 sccm, an N₂ flow that is between about 300 sccm and about 500sccm, and an Ar flow that is between about 300 sccm and about 500 sccmfor a period of time of between about 50 seconds and about 300 seconds.For the addition of other electronegative atoms to a metal layer, suchas Cl, Br, etc., one of skill in the art, upon reading the disclosureherein, can readily select the suitable process gases and processparameters.

Modifying Work Function of a Metal Layer

FIG. 7 sets forth a flow chart of process steps for modifying the workfunction of a metal layer in a metal gate structure, according tovarious embodiments of the disclosure. FIGS. 8A-8E are schematiccross-sectional views of a semiconductor device corresponding todifferent stages of the process of FIG. 7, according to variousembodiments of the disclosure.

A method 700 begins at step 701, in which high-k dielectric layer 203 isdeposited on interfacial oxide layer 202 as shown in FIG. 8A. High-kdielectric layer 203 may be formed via any suitable deposition methoddescribed above in conjunction with FIG. 2.

In step 702, p-type metal capping layer 204 is deposited on high-kdielectric layer 203, as shown in FIG. 8B. P-type metal capping layer204 may be formed via any suitable deposition method described above inconjunction with FIG. 2. In some embodiments, p-type metal capping layer204 includes vacancies (that may be similar to vacancies 213 in FIG. 2A)and/or electronegative atoms incorporated therein, such as suboxides orother non-stoichiometric compounds, by contamination present in theprocessing environment during the deposition process of step 702.

In optional step 703, an exposed surface 801, shown in FIG. 8B, isexposed to air. For example, in some embodiments, p-type metal cappinglayer 204 is deposited in one processing system, such as multi-chamberprocessing system 600 in FIG. 6, while the next processing step to beperformed on semiconductor substrate 201 is performed in a differentprocessing system. Thus, in such embodiments, semiconductor substrate201 is exposed to air after the deposition of metal nitride layer 204.In embodiments in which p-type metal capping layer 204 is deposited inone chamber of a multi-chamber processing system and step 704 isperformed in one or two other processing chambers of the samemulti-chamber processing system, and optional step 703 is not performed.

In step 704, a sequential plasma hydrogenation and oxidation process isperformed on surface 801 of p-type metal capping layer 204, as shown inFIG. 8C. The plasma hydrogenation and oxidation processes may besubstantially similar to the plasma hydrogenation and oxidationprocesses described above in conjunction with FIG. 4. Alternatively,instead of the oxidation process, a plasma process is performed onsurface 801 in step 704, in which other electronegative atoms besides Oatoms are included in p-type metal capping layer 204.

Thus, in step 704, surface 801 is exposed to plasma-excited hydrogenspecies generated in the plasma hydrogenation process, and some or alloxides present on surface 801 are reduced. In addition, in someembodiments, such plasma-excited hydrogen species can also reduce someor all oxygen (O) atoms present in the bulk material of p-type metalcapping layer 204. Furthermore, in step 704 surface 801 is exposed toplasma-excited electronegative species generated in a second plasmaprocess, thereby introducing electronegative atoms into p-type metalcapping layer 204 and forming stoichiometric combinations of theelectronegative atoms with atoms of p-type metal capping layer 204.

Alternatively, in some embodiments step 704 is not performed and method700 proceeds to step 705. In such embodiments, the plasma hydrogenationand oxygenation processes (or other electronegative plasma processes)are instead performed in step 708 on p-type metal gate electrode layer205.

In some embodiments, the plasma hydrogenation process of step 704 isperformed in the same processing chamber as the plasma oxidation processof step 704, for example in process chamber 400 of FIG. 4.Alternatively, the plasma hydrogenation process of step 704 is performedin a first processing chamber of a multi-chamber processing system,while the plasma oxidation process of step 704 is performed in a secondprocessing chamber of the same multi-chamber processing system. Ineither case, it is noted that surface 801 is not exposed to air betweenthe plasma hydrogenation process and the plasma oxidation process ofstep 704. Thus, in either embodiment, surface 801 is not exposed to airafter being exposed to the plasma-excited hydrogen species and beforebeing exposed to the plasma-excited nitrogen species.

In some embodiments, prior to performing the plasma hydrogenationprocess in a processing chamber, a plasma-based conditioning process isperformed in the processing chamber. In such embodiments, the processingchamber is treated with an oxygen-based, hydrogen-based, ornitrogen-based plasma without a substrate placed therein and before thesubstrate is treated via the above-described plasma hydrogenationprocess. Such plasma treatment of the process chamber prior tointroducing a substrate to the chamber is sometimes referred to as aplasma every wafer (PEW) process or PEW treatment.

In some embodiments, such a PEW process includes introducing one or morenon-oxygen-containing gases, such as O₂, N₂, NH₃, Ar, H₂, or anysuitable combination thereof, into the process chamber, and energizingthe one or more gases to form plasma. Alternatively, the PEW process mayinclude introducing plasma-containing radicals and/or ions of O, N, H,or NH₃, or any suitable combination thereof, into the process chamber,where the plasma is formed in a remote plasma source outside of theprocess chamber. In one embodiment, an NH₃ gas or a combination of NH₃and Ar gases is introduced into the process chamber. In anotherembodiment, H₂ gas or a combination of H₂ and Ar gases is introducedinto the process chamber. In yet another embodiment, N₂ gas or acombination of N₂ and Ar gases is introduced into the process chamber.In yet another embodiment, O₂ gas or a combination of O₂ and Ar gases isintroduced into the process chamber.

In some embodiments, during the PEW process, the one or more gasesintroduced into the processing chamber are energized by an RF powersource, such as RF power source 514 of FIG. 5. The RF power may bepulsed at 2% to 70% duty cycle and may range from about 100 W to about2500 W. The RF power may be a continuous wave ranging from about 100 Wto about 2500 W. The processing chamber may have a chamber pressureranging from about 10 mT to about 200 mT during the PEW treatment of theprocessing chamber. The process temperature, which in some embodimentsis defined as the temperature of the substrate support pedestal, such aspedestal 504 in FIG. 5, may range from about 20° C. to about 500° C. Ingeneral, the plasma formed during the PEW treatment may be formed by useof an inductively or capacitively coupled plasma.

In optional step 705, exposed surface 801 is exposed to air. Forexample, in some embodiments, the above-described sequentialhydrogenation and oxidation process is performed in one processingsystem, while the next processing step to be performed on semiconductorsubstrate 201 is performed in a different processing system. Thus, insuch embodiments, semiconductor substrate 201 is exposed to air afterthe deposition of metal nitride layer 204. In embodiments in which thesequential hydrogenation and oxidation process is performed in onechamber of a multi-chamber processing system and step 706 is performedin another processing chamber of the same multi-chamber processingsystem, optional step 705 is not performed.

In step 706, a thermal anneal process, such as a post-cap anneal, isperformed on semiconductor substrate 201, interfacial oxide layer 202,high-k dielectric layer 203, and p-type metal capping layer 204. Forexample, in some embodiments, a spike anneal process is performed instep 706, in which a peak temperature of about 600 to 900° C. isreached. The post-cap anneal is performed on partially formed metal gatestructure 200 to densify p-type metal capping layer 204.

In step 707, p-type metal gate electrode layer 205 is deposited on thetreated p-type metal capping layer 204, as shown in FIG. 8D, therebycompleting formation of metal gate structure 200. P-type metal gateelectrode layer 205 may be formed via any suitable deposition methoddescribed above in conjunction with FIG. 2.

In optional step 708, an exposed surface 802 of p-type metal gateelectrode layer 205 is exposed to plasma-excited hydrogen speciesgenerated in the plasma hydrogenation process, as shown in FIG. 8E. As aresult, some or all oxides or other electronegative atoms present onsurface 802 and within p-type metal gate electrode layer 205 arereduced. In addition, in step 708 surface 802 is exposed toplasma-excited electronegative species generated in a second plasmaprocess, thereby introducing electronegative atoms into p-type metalgate electrode layer 205 and forming stoichiometric combinations of theelectronegative atoms with atoms of p-type metal gate electrode layer205.

Typically, optional step 708 is performed on surface 802 when step 704is not performed on surface 801. In some embodiments, the plasmaprocesses of step 708 are substantially similar to the plasma processesof step 704.

FIG. 9 sets forth a bar graph 900 that compares measured flatbandvoltage (Vfb) shift for a p-type metal layer after various treatments.Specifically, bar graph 900 includes a measured flatband voltage 901 fora TiN capping layer that has undergone a post-cap anneal process and aplasma hydrogenation and oxidation process according to an embodiment ofthe disclosure. The TiN capping layer associated with measured flatbandvoltage 901 is substantially similar to p-type metal capping layer 204in FIG. 2. As is well-known in the art, if there is no charge present inthe oxide or at the oxide-semiconductor interface, the flatband voltagein a metal gate structure equals the work function difference betweenthe gate metal work function φ_(m) and the semiconductor work functionφ_(s) (each of which is in FIG. 1).

For reference, bar graph 900 also includes a measured flatband voltage902 for a similar TiN capping layer that has undergone a post-cap annealprocess but no plasma hydrogenation or oxidation process, as well as ameasured flatband voltage 903 for a similar TiN capping layer that hasnot undergone a post-cap anneal process or a plasmahydrogenation/oxidation process. As shown, measured flatband voltage 901is indicates an approximate 180 mV shift compared to measured flatbandvoltage 902, where no plasma hydrogenation and oxidation treatment hasoccurred. Similarly, measured flatband voltage 901 indicates anapproximate 110 mV shift compared to measured flatband voltage 903,where no plasma hydrogenation and oxidation treatment or post-cap annealtreatment has occurred.

The TiN capping layer associated with measured flatband voltage 901 issubstantially the same as the TiN capping layer associated with measuredflatband voltage 902, except that the plasma hydrogenation/oxidationprocess has been applied to the TiN capping layer associated withmeasured flatband voltage 901. Consequently, the 110 mV flatband voltageshift between measured flatband voltage 901 and measured flatbandvoltage 902 can be mostly or entirely attributed to a change in workfunction of the TiN capping layer by the plasma hydrogenation/oxidationprocess described herein.

In some embodiments disclosed herein, a sequential plasma process isemployed to enable the modification of the work function of a p-typemetal layer in a metal gate structure. The sequential plasma processincludes a plasma hydrogenation and a plasma process that includeselectronegative species. The sequential plasma process is performed on ap-type metal layer in a film stack, thereby replacing suboxides and/orother non-stoichiometrically combined electronegative atoms disposed onor within layers of the film stack with stoichiometrically combinedelectronegative atoms, such as O atoms. As a result, the work functionof the p-type metal layer can be modified without changing a thicknessof the p-type metal layer.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

1. A method of forming a transistor, the method comprising: depositing ahigh-k dielectric layer over a surface of a semiconductor material,wherein the surface of the semiconductor material has a first workfunction value; after depositing the high-k dielectric layer, depositinga p-type metal layer over the semiconductor material and the high-kdielectric layer, wherein the p-type metal layer has an exposed surfaceand a second work function value; exposing the exposed surface of thep-type metal layer to plasma-excited electronegative species to changethe first work function value to a third work function value, whereinthe third work function value is between the first work function valueand the second work.
 2. The method of claim 1, wherein the p-type metallayer comprises a metal capping layer that is deposited on the high-kdielectric layer.
 3. The method of claim 2, further comprising, afterexposing the exposed surface of the p-type metal layer to plasma-excitedspecies, depositing a different p-type metal layer on the exposedsurface.
 4. The method of claim 3, wherein the different p-type metallayer comprises a work function layer that is deposited on the metalcapping layer.
 5. The method of claim 3, further comprising, afterexposing the exposed surface of the p-type metal layer to plasma-excitedelectronegative species and prior to depositing the different p-typemetal layer on the exposed surface, exposing the exposed surface to air.6. The method of claim 1, wherein exposing the exposed surface of thep-type metal layer to plasma-excited electronegative species comprisesstoichiometrically adding atoms from the electronegative species to thep-type metal layer.
 7. The method of claim 1, wherein depositing thep-type metal layer comprises: depositing a first p-type metal layer onthe high-k dielectric layer; and depositing a second p-type metal layeron the first p-type metal layer, wherein exposing the exposed surface ofthe p-type metal layer to plasma-excited electronegative speciescomprises exposing an exposed surface of the second p-type metal layerto the plasma-excited electronegative species.
 8. The method of claim 1,wherein the plasma-excited electronegative species include atoms havinga Paulding electronegativity of at least about 2.5
 9. The method ofclaim 1, wherein the plasma-excited electronegative species include atleast one of an oxygen-containing species, a nitrogen-containingspecies, and a fluorine-containing species.
 10. The method of claim 1,wherein the p-type metal layer comprises a metal with a work functionvalue that is equal to or greater than the first work function value.11. The method of claim 1, further comprising, prior to exposing theexposed surface of the p-type metal layer to plasma-excitedelectronegative species, exposing the exposed surface to plasma-excitedhydrogen species to remove electronegative atoms from the p-type metallayer.
 12. The method of claim 11, wherein exposing the exposed surfaceto plasma-excited hydrogen species comprises forming vacancies in thep-type metal layer.
 13. The method of claim 12, wherein exposing theexposed surface of the p-type metal layer to plasma-excitedelectronegative species comprises filling the formed vacancies in thep-type metal layer with electronegative atoms.
 14. The method of claim11, wherein the exposed surface is not exposed to air after beingexposed to the plasma-excited hydrogen species and before being exposedto the plasma-excited electronegative species.
 15. The method of claim11, wherein the exposed surface is exposed to the plasma-excitedhydrogen species and to the plasma-excited electronegative species in asame processing chamber.
 16. The method of claim 1, wherein theplasma-excited electronegative species are formed by use of aninductively coupled plasma that is disposed adjacent to a surface of theexposed surface of the p-type metal layer.
 17. The method of claim 1,further comprising, prior to exposing the exposed surface of the p-typemetal layer to plasma-excited electronegative species, performing aplasma-based conditioning process on a process chamber in which theexposed surface is exposed to the plasma-excited electronegativespecies.
 18. The method of claim 17, wherein the plasma-basedconditioning process is performed on the process chamber when asemiconductor substrate on which the p-type metal layer is deposited isnot disposed within the process chamber.